1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits and particularly to those capable of detection and elimination of oscillation introduced in their internal voltage down conversion circuits.
2. Description of the Background Art
In recent years in LSI (Large Scale Integrated circuit) microfabrication insufficient breakdown voltages associated with transistors"" gate oxide film reduced in thickness are complemented by providing a voltage down conversion circuit in semiconductor integrated circuits to down-convert external power supply voltage. The down-converted power supply is used as an operating voltage to ensure reliability.
Generally it is desirable that the down-converted power supply be able to supply a constant voltage however operating conditions may vary. Accordingly, a conventional, internal power supply voltage down conversion circuit generates a constant reference voltage impervious to a variety of external power supply and fabrication process variations and in accordance the reference voltage generates a down converted voltage. This configuration is shown in FIG. 10, as standardized.
FIG. 10 is a circuit diagram specifically showing one example of the conventional, internal power supply voltage down conversion circuit.
As shown in FIG. 10, the conventional internal power supply voltage down conversion circuit includes a comparator detecting a difference in potential between the level of an internal voltage and the reference voltage and outputting a result of the comparison as a power supply drive signal DRV, and a feedback loop driven by signal DRV to control a drive transistor 17 formed by a p-channel MOS (Metal Oxide Semiconductor) transistor.
The comparator is a current mirror differential amplifier formed of n-channel MOS transistors 16 and 15 having their respective gates receiving internal voltage VDL and reference voltage VREF, respectively, with p-channel MOS transistors 13 and 14, having their sources connected to an external power supply node 6, as a load.
P-channel MOS transistors 13 and 14 configure a current mirror circuit, the former""s gate connected to the latter""s gate and drain.
Transistor 15 has its drain connected to that of transistor 13 and its source grounded.
Transistor 16 has its drain connected to the drain and gate of transistor 14 and the gate of transistor 13, its gate connected to an internal power supply node 2 and its source grounded.
The comparator has an output node, or the drain of transistor 15, connected to the gate of drive transistor 17.
Drive transistor 17 has its source connected to external power supply node 6, its gate to the comparator""s output node or the transistor 15 drain, and its drain connected to internal power supply node 2.
When drive transistor 17 receives at its gate the power supply drive signal DRV output from the comparator, drive transistor 17 accordingly supplies a current to internal power supply node 2 connected to its source.
If in this configuration a current is supplied to a load (not shown) connected to internal power supply node 2, drive transistor 17 acts as an impedance and the transistor""s drain voltage, or internal voltage VDL, varies negatively. When internal voltage VDL starts to be lower than reference voltage VREF, the comparator outputs power supply drive signal DRV of the logical low level. Drive transistor 17 receiving signal DRV of the low level at its gate turns on and starts to charge internal power supply node 2 while supplying the load (not shown) with a current. When the node has been charged to a level and internal voltage VDL starts to be larger than reference voltage VREF, the comparator outputs power supply drive signal DRV having a logical high level. Drive transistor 17 having received signal DRV of the high level at its gate turns off and stops charging the node.
Thus the internal power supply voltage down conversion circuit eliminates variation in level of internal voltage VDL.
Furthermore a conventional, internal power supply voltage down conversion circuit prevents impaired low power characteristics in a standby state. To achieve this, when a large amount of power is consumed or in an active state a large current is synchronously passed to a load to eliminate variation in internal voltage VDL and when a small amount of current is consumed or in a standby state a current that is supplied is minimized to allow the internal power supply voltage down conversion circuit to be of small power.
Thus the conventional, internal power supply voltage down conversion circuit having an ability to supply a current that alters in the standby or active state of the semiconductor integrated circuit can eliminate variation in internal voltage VDL between modes of operation accompanied by different amounts of power consumption.
However, the current supplying ability in each mode is maintained to be constant throughout the mode.
FIG. 11 is a diagram representing a waveform of internal voltage VDL in the conventional, internal power supply voltage down conversion circuit.
As represented in FIG. 11, internal voltage VDL in a normal operation state maintains a constant level in voltage with reference to reference voltage VREF. If power consumption is large and the current supplying ability is excessively increased, however, internal voltage VDL oscillates, having a large variation relative to reference voltage VREF, and this may result in the semiconductor integrated circuit being unable to operate normally.
However, the conventional, internal power supply voltage down conversion circuit provides the current supplying ability that is maintained to be constant throughout each of the active and standby state. As such, if internal voltage VDL oscillates, the current supplying ability does not vary and the oscillation continues disadvantageously.
Furthermore, in estimating a semiconductor integrated circuit including a conventional, internal power supply voltage down conversion circuit, whether internal voltage is in oscillation or not cannot be determined by means other than directly monitoring the level of the internal voltage for example via a tester. As such if the tester for example has an insufficient capacity it can fail to detect that the internal voltage is in oscillation.
One object of the present invention is therefore to ensure detection of an oscillation introduced by a current excessively supplied in an internal power supply voltage down conversion circuit.
Another object of the present invention is to provide a semiconductor integrated circuit capable of reducing a current supplying ability to spontaneously eliminate an oscillation detected in the internal power supply voltage down conversion circuit.
In accordance with present invention in one aspect a semiconductor integrated circuit operates receiving at an internal circuit an internal voltage from an internal power supply node, the internal voltage being lower than an external power supply voltage, and it includes: an internal power supply voltage down conversion circuit generating the internal voltage at the internal power supply node, the internal voltage being the external power supply voltage decreased to a reference voltage corresponding to a targeted level; and an oscillation detection circuit outputting an oscillation detection signal when a variation of no less than a predetermined variation is observed in the internal voltage relative to the reference voltage a predetermined number of times within a predetermined period of time.
In accordance with the present invention in another aspect when the internal power supply voltage down conversion circuit receives the oscillation detection signal from the oscillation detection circuit the internal power supply voltage down conversion circuit reduces an ability to supply a current to the internal power supply node.
In accordance with the present invention in still another aspect the oscillation detection circuit inactivates the shaped oscillation signal after the oscillation detection signal is output when a predetermined period of time elapses. An internal power supply voltage down conversion circuit includes a comparison circuit comparing an internal voltage with a reference voltage and outputting a signal corresponding to a result of the comparison, a drive transistor operative in response to the signal from the comparison circuit to supply an internal power supply node with a current to generate an internal voltage, and a first field effect transistor operative in response to the oscillation detection signal to electrically couple the drive transistor to the internal power supply node. When the oscillation detection signal inactivated is received the internal power supply voltage down conversion circuit turns on the first field effect transistor to resume supplying a current to the internal power supply node.
In accordance with the present invention in still another aspect the semiconductor integrated circuit further includes a test mode circuit receiving an oscillation detection signal from the oscillation detection circuit and outputting the oscillation detection signal to an external output node when the test mode circuit receives a test mode signal having a predetermined logical level.
Preferably the semiconductor integrated circuit further includes a test mode circuit receiving an oscillation detection signal from the oscillation detection circuit and outputting the oscillation detection signal to the internal power supply voltage down conversion circuit when the test mode circuit receives a test mode signal having a predetermined logical level. When the internal power supply voltage down conversion circuit receives the oscillation detection signal from the test mode circuit the internal power supply voltage down conversion circuit interrupts a current supplied to the internal power supply node and electrically shorts the internal power supply node.
Thus in accordance with the present invention in one aspect an oscillation detection circuit constantly compares an internal voltage level with an oscillation detection level set to be higher in potential than a reference voltage and when the internal voltage level has exceeded the oscillation detection level a predetermined number of times within a predetermined period an oscillation detection signal can be output to allow more ensured oscillation detection than when for example a tester is used to monitor the internal voltage.
Note that the oscillation detection level that is set to be higher in potential than the reference voltage can prevent erroneous detection as an oscillation of a variation in the internal voltage that is attributed to a factor other than oscillation such as noise.
Furthermore, the oscillation detection signal that is delayed and input as a counter reset signal can prevent erroneous detection for example of irregularly appearing noise.
Furthermore in accordance with the present invention in another aspect the oscillation detection signal that is fed back to the internal power supply voltage down conversion circuit can be used to reduce the down conversion circuit""s current supplying ability to spontaneously eliminate an oscillation in the down conversion circuit.
Furthermore in the present invention in still another aspect in the internal power supply voltage down conversion circuit the oscillation detection signal fed back from the oscillation detection circuit can be used to provide a reduced current supplying ability to spontaneously eliminate an oscillation and furthermore after a predetermined period of time has elapsed the oscillation detection signal can be inactivated to increase the reduced current supplying ability to prevent the internal voltage from dropping in level.
Note that the period of time between elimination of oscillation and recovery of the current supplying ability can be set by a delay stage to be a sufficiently long period to prevent possible, subsequent oscillation.
Furthermore in accordance with the present invention in still another aspect in a test mode of operation the oscillation detection signal can be monitored at an external output node to allow more ensured oscillation detection than when an internal voltage""s level is directly monitored.
Furthermore in accordance with the present invention in still another aspect in a test mode of operation an oscillation detection signal fed back to the internal power supply voltage down conversion circuit can be used to prevent a normal operation of a semiconductor integrated circuit to eliminate the necessity of monitoring any node to confirm an oscillation of an internal power supply.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.